1. Field of the Invention
The present invention relates to a Schottky gate field effect transistor (hereinafter referred to as xe2x80x9cSchottky gate FETxe2x80x9d), more specifically to a high-output-power Schottky gate FET for use in a higher frequency range.
2. Description of the Related Art
The mobility of GaAs is five to six times higher than in Si and the peak value of the saturated drift velocity of the electron transfer of the GaAs is about twice in Si. A semi-insulating substrate can be obtained by using the GaAs. The Schottky gate FET using the GaAs takes advantage of such features, and thus has been developed, while replacing an electron tube, as an active device used in the microwave band which is difficult to be realized by using the Si. Currently, the strong demand has been raised for the Schottky gate FET having a higher output power and operating in a higher frequency range. However, in the Schottky gate FET, the distortion characteristic is degraded during operation for an excessive input power. The Schottky gate FET for solving the above degradation is proposed in JP-A-2002-118122.
As shown in FIGS. 1A and 1B, the Schottky gate FET described in JP-A-2002-118122 includes a buffer layer 22, a channel layer 23, a source contact layer 24a and a drain contact layer 24b sequentially overlying a semi-insulating GaAs substrate 21. In and over the recess formed by removing part of the contact layers 24a and 24b, a gate electrode 25 having a T-shaped gate extension 26 and being in Schottky contact with the channel layer 23, and a source electrode 28 and a drain electrode 27 are formed. The gate extension 26 is in Schottky contact with the channel layer 23 and further extends toward above the drain, and each of the electrodes 27, 28 is in ohmic contact with the contact layers 24a and 24b. Part of the gate electrode 25, the contact layers 24a and 24b, the source electrode 28 and the drain electrode 27 are covered with a dielectric film 29.
In the structure shown in FIG. 1A, the following relationship (1) is satisfied between the length xe2x80x9cLgdxe2x80x9d of the field plate section 26 and the distance xe2x80x9cLrgdxe2x80x9d from the end of the recess near to the drain side to the point where the gate electrode 25, the dielectric film 29 and the channel layer 23 are in contact with one another.
Lgd=Lrgdxc2x1400 nmxe2x80x83xe2x80x83(1) 
The length xe2x80x9cLgdxe2x80x9d of the gate extension 26 is defined by the distance between the end of the gate electrode 25 near to the drain electrode 27 and the point where the gate electrode 25, the dielectric film 29 and the channel layer 23 are in contact with one another.
In the Schottky gate FET having thereon the gate extension wherein the above relationship is satisfied, the distortion generated by the excessive output power can be reduced. However, the following inconvenience may take place if the below relationship is satisfied.
Lgd=Lrgdxe2x88x92X (0xe2x89xa6Xxe2x89xa6400 nm) 
More specifically, the current is reduced after the operation of the transistor at the excessive power if the gate extension 26 overlies the drain contact layer 24b. This phenomenon can be hardly suppressed.
It is therefore an object of the present invention to provide a Schottky gate FET capable of effectively suppressing the phenomenon of current reduction after the operation of the transistor at the excessive power.
Thus, the present invention provides, in a first aspect thereof, a Schottky gate FET including a semi-insulating substrate, a channel layer overlying the semi-insulating substrate, a source contact layer and a drain contact layer formed on the channel layer and having a recess formed by removing part of the contact layers, a gate electrode formed over the recess and being in Schottky contact with the channel layer, a source electrode and a drain electrode in ohmic contact with the source contact layer and the drain contact layer, respectively, and a dielectric film formed between the gate electrode and the drain electrode, wherein the gate electrode includes a gate extension which is in contact with the dielectric film and extend to overlie at least part of the drain electrode and the drain contact layer.
The present invention provides, in a second aspect thereof, a Schottky gate FET including a semi-insulating substrate, a channel layer overlying the semi-insulating substrate, a source contact layer and a drain contact layer formed on the channel layer and having a recess formed by removing part of the contact layers, a gate electrode formed over the recess and being in Schottky contact with the channel layer, a field plate separated from the gate electrode and electrically connected thereto, a source electrode and a drain electrode in ohmic contact with the source contact layer and the drain contact layer, respectively, and a dielectric film formed between the gate electrode and the drain electrode, wherein the field plate overlies at least part of the drain electrode and the drain contact layer sandwiching the dielectric film.
In accordance with the Schottky gate FET of the present invention, since the gate extension or the field plate overlies at least part of the drain contact layer and the drain electrode, the phenomenon can be suppressed that the dielectric film is charged in a negative polarity due to the electrons injected into the dielectric film around the gate extension or the field plate during the operation at an excessive output power to reduce the current after the transistor operation. In this manner, an inconvenience can be averted that the operation of the circuit module mounting the Schottky gate FET departs from the rating to prevent the circuit module from non-usable. Further, in the second aspect, the parasitic capacitance between the field plate and the channel layer can be reduced.
The above and other objects, features and advantages of the present invention will be more apparent from the following description.